GS8161Z36DGT-200V

Name: GSI Technology GS8161Z36DGT-200V
Brand: GSI Technology
SKU: 464-GS8161Z36DGT200V
Price: 35.69 CHF
Availability: OutOfStock

Images are for reference only
See Product Specifications

Mouser No:

464-GS8161Z36DGT200V

Mfr. No:

GS8161Z36DGT-200V

Mfr.:

GSI Technology

Description:

SRAM 1.8/2.5V 512K x 36 18M

Datasheet:

GS8161Z36DGT-200V Datasheet (PDF)

ECAD Model:

Download the free Library Loader to convert this file for your ECAD Tool. Learn more about the ECAD Model.

More Information

Learn more about GSI Technology GS8161Z36DGT-200V

.hidden-for-nojs { display: none; } .pull-right-nojs { justify-content: flex-end; }

Product Attribute	Attribute Value	Select Attribute
Manufacturer:	GSI Technology
Product Category:	SRAM
RoHS:
Memory Size:	18 Mbit
Organisation:	512 k x 36
Access Time:	6.5 ns
Maximum Clock Frequency:	200 MHz
Interface Type:	Parallel
Supply Voltage - Max:	2.7 V
Supply Voltage - Min:	1.7 V
Supply Current - Max:	205 mA, 210 mA
Minimum Operating Temperature:	0 C
Maximum Operating Temperature:	+ 70 C
Mounting Style:	SMD/SMT
Package/Case:	TQFP-100
Packaging:	Tray
Brand:	GSI Technology
Memory Type:	SDR
Moisture Sensitive:	Yes
Product Type:	SRAM
Series:	GS8161Z36DGT
Factory Pack Quantity:	18
Subcategory:	Memory & Data Storage
Tradename:	NBT SRAM
Type:	NBT

Products found:

To show similar products, select at least one checkbox

Select at least one checkbox above to show similar products in this category.

Attributes selected: 0

Filter Document:

Datasheet

GS8161Z36DGT-200V Datasheet (PDF)

This functionality requires JavaScript to be enabled.

Compliance Codes

CNHTS:: 8542319090
CAHTS:: 8542320041
USHTS:: 8542320041
JPHTS:: 854232029
KRHTS:: 8542321020
TARIC:: 8542324500
MXHTS:: 8542320201
ECCN:: 3A991.b.2.b

Origin Classifications

Country of Origin:: Not available
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

NBT SRAMs

GSI Technology NBT SRAMs are 144Mbit and 288Mbit Synchronous Static SRAMs that utilize all available bus bandwidth. The SRAMs achieve this by eliminating the need to insert deselect cycles when the device is switched from read to write cycles. The devices' simplified interface is designed to use a data bus's maximum bandwidth. Because it is a synchronous device, address, data inputs, and read/write control inputs are captured on the rising edge of the input clock.