GS8342Q09BGD-250I

Name: GSI Technology GS8342Q09BGD-250I
Brand: GSI Technology
SKU: 464-GS8342Q09BGD250I
Price: 42.61 CHF
Availability: OutOfStock

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Mouser No:

464-GS8342Q09BGD250I

Mfr. No:

GS8342Q09BGD-250I

Mfr.:

GSI Technology

Description:

SRAM 1.8 or 1.5V 4M x 9 36M

Datasheet:

GS8342Q09BGD-250I Datasheet (PDF)

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	GSI Technology
Product Category:	SRAM
RoHS:
Memory Size:	36 Mbit
Organisation:	4 M x 9
Access Time:	450 ps
Maximum Clock Frequency:	250 MHz
Interface Type:	Parallel
Supply Voltage - Max:	1.9 V
Supply Voltage - Min:	1.7 V
Supply Current - Max:	675 mA
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Mounting Style:	SMD/SMT
Package/Case:	BGA-165
Packaging:	Tray
Brand:	GSI Technology
Memory Type:	DDR
Moisture Sensitive:	Yes
Product Type:	SRAM
Series:	GS8342Q09BGD
Factory Pack Quantity:	15
Subcategory:	Memory & Data Storage
Tradename:	SigmaQuad-II
Type:	SigmaQuad-II

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Datasheet

GS8342Q09BGD-250I Datasheet (PDF)

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Compliance Codes

CNHTS:: 8542319090
CAHTS:: 8542320041
USHTS:: 8542320041
JPHTS:: 854232029
KRHTS:: 8542321020
TARIC:: 8542324500
MXHTS:: 8542320201
ECCN:: 3A991.b.2.b

Origin Classifications

Country of Origin:: Taiwan
Assembly Country of Origin:: Not available
Country of Diffusion:: Not available

The country is subject to change at the time of shipment.

SigmaQuad-II SRAMs

GSI Technology SigmaQuad-II SRAMs feature built-in compliance with the SigmaQuad-II SRAM pinout standard for Separate I/O synchronous SRAMs. The SigmaQuad-II are 301,989,888-bit (288Mb) SRAMs. The GS82582D18/36GE SigmaQuad SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.

Quad SRAMs

GSI Technology Quad SRAMs combine capacity and performance with the ability to transfer four beats of data (two beats per data bus) in a single clock cycle. SigmaQuad SRAMs are synchronous memories with separate read and write data buses with unequaled transaction rates by competitors.